FPGA & Digital Design
ECE student at USC (class of 2027) building things close to the metal. Most of my work lives in SystemVerilog targeting Xilinx and Intel parts — from AI accelerators to pipelined RISC-V cores. When I'm not staring at waveforms I'm probably writing CANbus firmware for our FSAE car.
I care about clean design, good timing closure, and writing testbenches that actually catch bugs. I also think hardware engineers should have nice websites.
Research on Large Concept Models and Mixture of Experts AI architectures. Designing hardware-software co-design solutions implemented in Verilog RTL and deployed on FPGA.
Writing CANbus firmware on STM32 for motor controller comms, ADC/DAC data acquisition, and FreeRTOS multitasking for concurrent sensor and CAN communication.
Pipelined systolic array achieving 1 output/cycle for FP16 matrix multiplication. Parameterizable N×N arrays with AXI4 BRAM interface. Synthesized and closed timing in Vivado.
RV32I + Zicsr processor with hazard detection, data forwarding, GShare branch prediction, SV32 virtual memory, and UART I/O. Passes official compliance tests and boots xv6.
AXI4-compliant slave (1R/1W per cycle), formally verified with SymbiYosys. Full UVM environment with driver, monitor, scoreboard, and constrained random tests in QuestaSim.