An AXI4-compliant slave peripheral capable of sustaining 1 read and 1 write per cycle, with both formal and simulation-based verification.
The slave implements the full AXI4 handshake protocol with proper ordering guarantees. Designed for integration into larger SoC designs where protocol compliance is critical.
Used SymbiYosys for formal property checking, proving protocol compliance and absence of deadlocks across all reachable states.
Built a complete UVM verification environment in QuestaSim: driver, monitor, scoreboard, sequences, and coverage collectors. Constrained random tests verified handshake compliance, burst ordering, and edge cases under randomized traffic patterns.