A pipelined processor implementing the RV32I and Zicsr instruction sets, complete with hazard detection, branch prediction, and virtual memory.
Classic 5-stage pipeline (IF/ID/EX/MEM/WB) with full data forwarding and a GShare branch predictor for reducing pipeline stalls. The memory subsystem uses SV32 virtual memory with a unified address space.
Includes a CSR register file with privilege levels and trap/interrupt handling for exception management. A memory-mapped UART peripheral provides serial I/O.
Automated verification flow using Python and Tcl to compile hex test files and run batch simulations in Vivado. Passed the full suite of official RISC-V compliance tests.
Successfully boots and runs xv6 operating system, confirming correct behavior of the pipeline, memory system, interrupt handling, and privilege transitions.